1. Field of the Invention
The present invention relates to a semiconductor device and production method thereof and in particular, to a semiconductor device having an electromigration resistance and production method thereof.
2. Description of the Related Art
In a semiconductor device, a wiring layer (a groove wiring and a contact plug) is formed for connecting elements formed on a semiconductor substrate each other and connecting elements with a peripheral circuit. Normally, such a wiring layer is made from an aluminium alloy (such as AlCu (aluminium copper) and AlSiCu (aluminium silicon copper).
As the semiconductor device size becomes smaller, a wiring and a contact hole are made smaller. Moreover, in order to improve the semiconductor device performance, it is required to use a wiring having a lower resistance value. A wiring layer having such a low resistance is made from Cu (copper).
FIG. 5 is a cross sectional view showing a region having the aforementioned wiring layer (wiring layer formation region).
As shown in FIG. 5, the wiring layer formation region includes a semiconductor substrate 21, a insulation layer 22, a barrier metal 23, a seed layer 24, and a wiring layer 25.
The semiconductor substrate 21 is, for example, a Si (silicon) substrate on which elements (not depicted) are formed.
The insulation layer 22 is formed on the semiconductor substrate 21 and has a groove 22a for forming a wiring layer 25. The insulation layer 22 is formed, for example, from SiO2 (silicon dioxide) for insulation between the wiring layer 25 and the other wiring layer (not depicted).
The barrier metal 23 is formed on an inner wall of the groove 22a formed in the insulation layer 22, so as to prevent atoms constituting the wiring layer 25 from diffusion into the insulation layer 22. Moreover, the barrier metal 23 is formed, for example, from TiN (titanium nitride), Ta (tantalum), NaN (tantalum nitride), or the like.
The seed layer 24 is formed on the barrier metal 23 formed on the inner wall of the groove 22a and serves as a kernel for crystal growth of the wiring layer 25. Moreover, the seed layer 24 is formed, for example, from Copper.
The wiring layer 25 is formed on the seed layer 24 to fill the groove 22a. As has been described above, the wiring layer 25 connects the elements formed on the semiconductor substrate 21 one another and connects the elements with a peripheral circuit. Moreover, the wiring layer 25 is formed, for example, from copper.
Next, explanation will be given on the formation of the wiring layer formation region having the aforementioned configuration.
FIG. 6 is a cross sectional view showing a formation procedure of the wiring layer formation region.
Firstly, as shown in FIG. 6(a), the semiconductor substrate 21 is covered by the insulation layer 22 formed by the CVD (chemical vapor phase deposition) method or the like, and a groove 22a is formed by photolithography or etching in a predetermined region of the insulation layer 22, for formation of the wiring layer 25.
After the groove 22a is formed, as shown in FIG. 6(b), for example, using anisotropic sputtering, the barrier metal 23 and the seed layer 24 are formed in this order on the insulation layer 22 including the inner wall 22a. It should be noted that it is possible to employ the anisotropic technique disclosed Japanese Patent Publication No. 6-140359, Japanese Patent Publication No. 7-292474, and Japanese Patent Publication No. 10-259480.
After formation of the barrier metal 23 and the seed layer 24, as shown in FIG. 6(c), a Cu layer 25a is formed on the seed layer 24 by electrolytic plating.
After this, using the CMP (chemical mechanical polishing) method or the like. the barrier metal 23, the seed layer 24, and the Cu layer 25a are polished so as to expose a surface of the insulation layer 22. Thus, the wiring layer 25 is formed to complete the wiring layer formation region shown in FIG. 5.
In the formation of the wiring layer 25 (Cu layer 25a) by the electrolytic plating, since the wiring layer 25 almost uniformly grows on the seed layer 24, there is a case that a sheath (seam) 26 remains in the wiring layer 25 as shown in FIGS. 6(c) and 6(d). If the sheath 26 is present in the wiring layer 25, the sheath is clogged with abrasive (silica and alumina particles) during the polishing by the CMP method. This significantly lowers the reliability of the wiring layer 25 and the yield of the semiconductor device production.
As a method to remove the aforementioned sheath 26, for example, there is an electrolytic plating method called bottom-up fill. This bottom-up fill is disclosed, for example, in the xe2x80x9cCu Haisen Gizyutu no Saisinno Tenkai (New Development of Cu Wiring Technology)xe2x80x9d Realize Co., Ltd. p. 23 [1] and xe2x80x9cThe Role of Additives an Electroplating of Void-Free Cu in Sub-micron Damascene Featuresxe2x80x9d [2].
The bottom-up fill is a technique for increasing the film formation speed from the bottom of the groove (hole) by putting an additive into the plating liquid and periodically applying field reversing. As shown in FIG. 7(a) and FIG. 7(b), in the bottom-up fill, the growth speed of the Cu layer (wiring layer 25) 25a from the bottom of the groove 22a is higher than the growth speed from the insulation layer 22 or the side wall of the groove 22a. Accordingly, the sheath 26 present in the Cu layer 25a is short as shown in FIG. 7(c). Consequently, after the barrier metal 23, the seed layer 24, and the Cu layer 25a are polished by the CMP method, the sheath 26 may be absent from the wiring layer 25 as shown in FIG. 27(d).
In the technique forming the wiring layer 25 by the electrolytic plating, there is a problem that electromigration of the wiring layer 25 is easily caused.
The electromigration is described, for example, in the xe2x80x9cCu Damascene Interconnects with Crystallographic Texture Control and its Electromigration Performancexe2x80x9d, Kazuhide Abe et al. 1998, IEEE IRPS, p 342 [3]. Document [3] shows an experiment result that the electromigration is not caused easily when the (1 1 1) orientation of the Cu wiring layer is strong, and the electromigration is easily caused when the (1 1 1) orientation of the Cu wiring layer is weak, i.e., other than the (1 1 1) orientation is strong.
In the production method shown in FIG. 6, since the crystal orientation of the seed layer 24 is not controlled, there is a case that other than the (1 1 1) orientation is dominant in the wiring layer 25 growing on the seed layer 24. When other than the (1 1 1) orientation is dominant in the wiring layer 25, electromigraiton is easily caused, which results in lowering operation reliability of a semiconductor device produced.
It is therefore an object of the present invention to provide a semiconductor device which can improve the operation reliability. Another object of the present invention is to provide a semiconductor device production method suppressing electromigration.
In order to achieve the aforementioned object, the semiconductor device production method according to an aspect of the present invention comprises steps of: forming an insulation layer on a substrate for insulation between wires; forming a groove in a predetermined region of the insulation layer for forming a wiring layer; forming a barrier layer on an inner wall of the groove for preventing diffusion of atoms constituting the wiring layer, into the insulation layer; forming a seed layer serving as a kernel for crystal growth when forming the wiring layer in such a manner that substantially (1 1 1) orientation can be obtained; and forming a wiring layer having a substantially (1 1 1) orientation on the seed layer so as to bury the groove.
According to this invention, by making orientation of the seed layer substantially (1 1 1), the wiring layer formed there on can also have substantially (1 1 1) orientation. Accordingly, electromigration is not easily caused, improving the operation reliability of the semiconductor device produced.
The seed formation step may includes a step of forming the seed layer on the barrier layer at the bottom of the groove.
Thus, in the groove, the wiring layer grows only in one direction and no seam is present in the wiring layer formed.
The aforementioned seed formation step may include a step of forming the seed layer by anisotropic sputtering.
The seed formation step may include an etching step for etching and removing the seed layer formed on the side wall of the groove.
The seed formation step may include a step of forming the seed layer from a material not melted by a plating liquid.
The seed formation step may include a step of forming the seed layer from copper and the wiring formation step may include a step of forming the wiring layer from copper.
According to another aspect of the present invention, there is provided a semiconductor device comprising: an insulation layer formed on a substrate and having a groove for forming a wiring layer in a predetermined region; a barrier layer formed on an inner wall of the groove for preventing diffusion of atoms constituting the wiring layer, into the insulation layer; a seed layer formed on the barrier layer so as to serve as a kernel of crystal growth when forming the wiring layer and having substantially (1 1 1) orientation; and a wiring layer formed on the seed layer so as to bury the groove and having substantially (1 1 1) orientation.
According to this invention, the wiring layer has substantially (1 1 1) orientation and electromigration is not easily caused. Accordingly, the semiconductor device has a high operation reliability.
The seed layer may be formed on the barrier layer at the bottom of the groove.
The seed layer may be formed from coper, and the wiring layer may be formed from copper.